发现心仪岗位

The Opportunity

You will build the heartbeat of our AI accelerator. While our compilers generate the "what" (the neural network graph), the Runtime determines the "how" (execution). You will write the low-level C/C++ code that manages DMA engines, synchronizes parallel cores, and drives high utilization on our 4-PE AISoC while maintaining correctness and stability.

Key Responsibilities

· Pipeline Orchestration: Implement the on-device scheduler that coordinates data transfers (DMA) and compute tasks. You will solve classic "producer-consumer" problems in silicon.

· Memory Management: Build the allocator that manages tight on-chip SRAM (TCM). You decide where every tensor lives and when it dies.

· Hardware Abstraction (HAL): Implement the low-level HAL and intrinsic wrappers used by our runtime and kernel library (no kernel-mode driver experience required).

· Consistency & Visibility: Define and enforce explicit memory visibility protocols between cores/TCM/DMA (clean/flush + fence/events) to prevent stale data reads on our non-coherent system.

· Debug & Profiling: Create the tools that tell us why the chip is stalling (trace markers, cycle counters).

What We Will Teach You

· Our specific DMA descriptor model and event synchronization hardware.

· How to manage memory visibility (cache maintenance) on a non-coherent architecture.

· The internal workings of our on-device scheduling framework.

Must-Have Qualifications

· Strong proficiency in C/C++ (you understand pointers, memory layout, and the stack vs. heap).

· Academic or project experience with Operating Systems concepts (mutexes, race conditions, context switching).

· Fearlessness in debugging: You don't just stare at a segfault; you attach a debugger and find the root cause.

Nice-to-Have

· Experience with embedded systems (Raspberry Pi, STM32, or bare-metal RISC-V).

· Knowledge of Python (for building test scripts to drive your C++ runtime).